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SMBus/I 2 C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
Serial Interface
Serial Addressing
The MAX7306/MAX7307 operate as a slave that sends
and receives data through an I 2 C-compatible, 2-wire
interface. The interface uses a serial-data line (SDA)
and a serial-clock line (SCL) to achieve bidirectional
communication between master(s) and slave(s). A
master (typically a microcontroller) initiates all data
transfers to and from the MAX7306/MAX7307 and gen-
erates the SCL clock that synchronizes the data trans-
fer (see Figure 8).
The MAX7306/MAX7307 SDA line operates as both an
input and an open-drain output. A 4.7k Ω (typ) pullup
resistor is required on SDA. The MAX7306/MAX7307
SCL line operates only as an input. A 4.7k Ω (typ) pullup
resistor is required on SCL if there are multiple masters
on the 2-wire interface, or if the master in a single-mas-
ter system has an open-drain SCL output.
Each transmission consists of a START condition (see
Figure 9) sent by a master, followed by the MAX7306/
MAX7307 7-bit slave address plus R/ W bit, a register
address byte, one or more data bytes, and finally a STOP
condition (see Figure 9).
SDA
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (see Figure 9).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(see Figure 10).
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipient
uses to acknowledge receipt of each byte of data (see
Figure 11). Thus, each effectively transferred byte
requires 9 bits. The master generates the 9th clock pulse,
and the recipient pulls down SDA during the acknowledge
clock pulse, so the SDA line is stable low during the high
period of the clock pulse. When the master is transmitting
to the MAX7306/MAX7307, the devices generate the
acknowledge bit because the MAX7306/MAX7307 are the
t LOW
t SU,DAT
t HD,DAT
t SU,STA
t HD,STA
t SU,STO
t BUF
SCL
t HD,STA
t R
t HIGH
t F
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
RESET
t WL(RST)
Figure 8. 2-Wire Serial Interface Timing Details
SDA
SDA
SCL
S
START
P
STOP
SCL
CONDITION
Figure 9. Start and Stop Conditions
CONDITION
DATA LINE STABLE; CHANGE OF DATA
DATA VALID
ALLOWED
Figure 10. Bit Transfer
18
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